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HV301/HV311 Hot Swap Controller (Negative Supply Rail)
Features
10V to 90V Operation Built-in "normally on" turn-on clamp eliminates components UV/OV Lock Out & Power-on-Reset for Debouncing Sense resistor program ground circuit breaker Programmable circuit breaker holdoff Inrush control using either: i) servo or ii) feedback cap Feedback to Ramp pin means no Gate clamp needed Application solution for input voltage step (diode "ORing") Programmable Auto-Retry (tens of seconds if desired) Auto-Retry or Latched Operation Enable through Open Drain interface to UV or OV Low Power, <0.6mA PWRGD Flag Operation, <0.4mA Sleep Mode Small SOIC-8 Package
HV301/HV311
Ordering Information
A c t i v e St at e o f Po w er Go o d Si g n al HIGH LOW Pac k ag e Op t i o n s 8 Pin SO HV301LG HV311LG
Applications

Typical Application Circuit
GND 8 VDD PWRGD / PWRGD R1 487k R2 6.81k R3 9.76k VEE 4 SENSE 5 GATE 6 C1 10nF -48V R4 12.5m Q1 IRF530 -48V RAMP 7 C2 1
ed nd e m om igns! ec tR o es N D ew rN Fo
General Description
The Supertex HV301 and HV311 Hot Swap Controllers provide control of power supply connection during insertion of cards or modules into live backplanes. They may be used in systems where active control is implemented in the negative lead of supplies ranging from 10V to 90V. -48V Central Office Switching -24V Cellular and Fixed Wireless Systems -24V PBX Systems Line Cards -48V Powered Ethernet for VoIP Distributed Power Systems Power Supply Control +48V Storage Networks Electronic Circuit Breaker During initial power application the gate of the external pass device is clamped low to suppress contact bounce glitches by a "normally on" circuit which does not require initialization of the IC. Thereafter the UV/OV supervisors and power-on-reset work together to suppress gate turn on until mechanical bounce has ended. The HV301/311 then control the current inrush limit to a programmed level using one of two possible methods, i) servo control or ii) a drain to ramp capacitor. The above methods eliminate the need for extra hold-off or current limiting components. The devices also include an electronic circuit breaker, programmed by a sense resistor. After the load capacitance has fully charged, the HV301/311 will transition into a low power mode, and enable the open drain PWRGD. In low power mode the HV301/311 continues to monitor the input voltage and monitor the current level. If a load fault occurs, the electronic circuit breaker will trip, the pass element will be turned off, and the PWRGD will return to an
(continued on Page 3)
3
ENABLE / ENABLE UV
+5V
Waveforms
Drain 50V/div VIN 50V/div
2
OV
HV301/ HV311
Cload DC/DC PWM CONVERTER COM
0.85nF
Gate 5.00V/div
Iinrush 500mA/div
NOTES: 1. 2. 3. 4. Undervoltage Shutdown (UV) set to 35V. Overvoltage Shutdown (OV) set to 65V. Current Limit set to ~1A. CB set to 8A.
5.00ms/div
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1
HV301/HV311
Electrical Characteristics
Symbol Parameter
(-10V - VEE - -90V, -40C - +85C unless otherwise noted)
Min Typ Ma x Units Conditions
Supply (Referenced to VDD pin)
VEE IEE IEE Supply Voltage Supply Current Sleep Mode Suppy Current -90 600 400 -10 700 450 V A A VEE = -48V, Mode = Limiting VEE = -48V, Mode = Sleep
OV and UV Control (Referenced to VEE pin)
VUVH VUVL VUVHY IUV VOVH VOVL VOVHY IOV UV High Threshold UV Low Threshold UV Hysteresis UV Input Current OV High Threshold OV Low Threshold OV Hysteresis OV Input Current 1.26 1.16 100 1.0 1.26 1.16 100 1.0 V V mV nA V V mV nA VOV = VEE + 0.5V VUV = VEE +1.9V Low to High Transition High to Low Transition Low to High Transition High to Low Transition
Current Limit (Referenced to VEE pin)
VSENSE-CL VSENSE-CB
Current Limit Threshold Voltage
Circuit Breaker Threshold Voltage
40 80
50 100
60 120
mV mV
VUV = VEE + 1.9V, VOV = VEE + 0.5V VUV = VEE + 1.9V, VOV = VEE + 0.5V
Gate Drive Output (Referenced to VEE pin)
VGATE IGATEUP IGATEDOWN Maximum Gate Drive Voltage Gate Drive Pull-Up Current Gate Drive Pull-Down Current 8.5 500 40 10 12 V A mA VUV = VEE + 1.9V, VOV = VEE + 0.5V VUV = VEE + 1.9V, VOV = VEE + 0.5V VUV = VEE, VOV = VEE + 0.5V
Ramp Timing Control (Test Conditions: CLOAD=100mF, CRAMP=10nF, VUV=VEE+1.9V, VOV=VEE+0.5V, External MOSFET is IRF530*)
IRAMP tPOR tRISE tLIMIT tPWRGD VRAMP tSTARTLIMIT tCBTRIP tAUTO Ramp Pin Output Current Time from UV to Gate Turn On Time from Gate Turn On to VSENSE Limit Duration of Current Limit Mode Time from Current Limit to PWRGD Voltage on Ramp Pin in Current Limit Mode Start Up Time Limit Circuit Breaker Delay Time Automatic Restart Delay TIme 80 2.0 12 2.0 400 5.0 5.0 3.6 100 120 5.0 10 A ms s ms ms V ms s s
May be exteneded by external RC circuit
VSENSE = 0V (See Note 1)
(See Note 2)
Power Good Output (Referenced to VEE pin)
VPWRGD(hi) VPWRGD(lo)
Applied voltage to PWRGD PWRGD Low Voltage
90 0.5 0.8
V V
PWRGD=Inactive IPWRGD = 1mA, PWRGD=Active
Dynamic Characteristics
tGATEHLOV OV Comparator Transition tGATEHLUV UV Comparator Transition 500 500 ns ns
Note 1: This timing depends on the threshold voltage of the external N-Channel MOSFET. The higher its threshold is, the longer this timing. Note 2: This voltage depends on the characteristics of the external N-Channel MOSFET. Vth = 3V for an IRF530. * IRF530 is a registered trademark of International Rectifier.
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2
HV301/HV311
General Description, cont'd.
inactive state. Thereafter a programmable auto-retry timer will hold the device off to allow the pass element to cool before resetting and restarting. The auto-retry can be disabled using a single resistor if desired. The HV301/311 includes a current mode servo-circuit which can be used as a return to limit during input voltage steps such as would be seen in a diode "ORed" situation when power switches back to regulated supply from battery operation. The HV301/311 allows independent programming of the trigger level of this phenomenon so that it may be set at a different level to the current limit level if desired. Under all circumstances the maximum servo period is limited to 100ms to protect the pass element.
PWRGD Logic
Mo d el HV301 Co n d i t i o n INACTIVE (Not Ready) ACTIVE (Ready) INACTIVE (Not Ready) ACTIVE (Ready) PWRGD 0 1 1 0 VEE HI Z HI Z VEE
HV311
Absolute Maximum Ratings
VEE reference to VDD pin VPWRGD referenced to VEE Voltage VUV and VOV referenced to VEE Voltage Operating Ambient Temperature Operating Junction Temperature Storage Temperature Range +0.3V to -100V -0.3V to +100V -0.3V to +12V -40C to +85C -40C to +125C -65C to +150C
Pinout
PWRGD (HV301) PWRGD (HV311) OV UV VEE 1 2 3 4 8 7 6 5 VDD RAMP GATE SENSE
Pin Description
PWRGD - The Power Good Output Pin is held inactive on initial power application and will go active when the external MOSFET is fully turned on. This pin may be used as an enable control when connected directly to a PWM power module. OV - This Over Voltage sense pin, when raised above its high threshold will immediately cause the GATE pin to be pulled low. The GATE pin will remain low until the voltage on this pin falls below the low threshold limit, initiating a new start-up cycle. UV - This Under Voltage sense pin, when below its low threshold limit will immediately cause the GATE pin to be pulled low. The GATE pin will remain low until the voltage on this pin rises above the high threshold limit, initiating a new start-up cycle. VEE - This pin is the negative terminal of the power supply input to the circuit. VDD - This pin is the positive terminal of the power supply input to the circuit. RAMP - This pin provides a current output so that a timing ramp voltage is generated when a capacitor is connected. GATE - This is the Gate Driver Output for the external NChannel MOSFET. SENSE - The current sense resistor connected from this pin to VEE Pin programs the circuit breaker trip limit.
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HV301/HV311
Functional Block Diagram
UV
C
Regulator & POR
VIN
Vbg
UVLO
OV
C
Logic
P U L L H I G H
PWRGD = HV301 PWRGD = HV311
~9.8V
C
Latch High Sleep
D I S A B L E
VDD
2Vbg
10A
1:2 mirror buffer
GATE
RAMP SENSE
Transconductor
Transconductor
5k
gm
5k VEE
Clamp Mechanism
Functional Description
Insertion into Hot Backplanes Telecom, data networks and some computer applications require the ability to insert and remove circuit cards from systems without powering down the entire system. All circuit cards have some filter capacitance on the power rails, which is especially true in circuit cards or network terminal equipment utilizing distributed power systems. The insertion can result in high inrush currents that can cause damage to connector and circuit cards and may result in unacceptable disturbances on the system backplane power rails. The HV301 and HV311 are designed to facilitate the insertion of these circuit cards or connection of terminal equipment by eliminating these inrush currents and powering up these circuits in a controlled manner after full connector insertion has been achieved. The HV301 or HV311 is intended to provide this function on supply rails in the range of 10 to 90 Volts. Description of Operation During initial power application, a unique proprietary circuit holds off the external MOSFET, preventing an input glitch while an internal regulator establishes an internal operating voltage of approximately 10V. Until the proper internal voltage is achieved all circuits are held reset, the PWRGD output is inactive and the gate to source voltage of the external MOSFET is clamped low. 4
Once the internal under voltage lock out (UVLO) has been satisfied, the circuit checks the input supply under voltage (UV) and over voltage (OV) sense circuits to ensure that the input voltage is within programmed limits. These limits are determined by the selected values of resistors R1, R2 and R3, which form a voltage divider. Assuming the above conditions are satisfied and while continuing to hold the PWRGD output inactive and the external MOSFET GATE voltage low, the current source feeding the RAMP pin is turned on. The external capacitor connected to it begins to charge, thus starting an initial time delay determined by the value of the capacitor. During this time if the OV or UV limits are exceeded, an immediate reset occurs and the capacitor connected to the RAMP pin is discharged. When the voltage on the RAMP pin reaches an internally set threshold voltage, the gate drive circuit begins to turn on the external MOSFET. In servo mode, once the gate threshold is reached, the resulting output current generates a voltage drop on the sense resistor connected between the SENSE and VEE pins, causing a decrease in the available current charging the capacitor on the RAMP pin. This continuous feedback mechanism allows the output current to rise inverse exponentially over a period of a few hundred microseconds to the sense resistor programmed current limit set point. When the voltage drop on the sense resistor reaches 50mV the
A092605
HV301/HV311
Functional Description, cont'd.
RAMP pin current is reduced to zero and the voltage on the RAMP pin will be fixed, indicating that the circuit is in current limit mode. Depending on the value of the load capacitor and the programmed current limit, charging may continue for some time, but may not exceed a nominal 100ms preset time limit. Once the load capacitor has been charged, the output current will drop, reducing the voltage on the SENSE pin, which in turn will increase the RAMP pin current, thus causing the voltage on the capacitor connected to the RAMP pin to continue rising, thereby providing yet another programmed delay. If due to output overload conditions during startup, PWRGD does not achieve an active state within 100ms or the Circuit Breaker is tripped, the circuit is reset, pulling down the GATE to VEE, discharging the capacitor connected to the RAMP pin, changing PWRGD to an inactive state. A timeout or circuit breaker fault will initiate an Auto-Retry if enabled. On the other hand, in feedback capacitor mode, a current source of 10A from the RAMP pin limits the dv/dt of the feedback capacitor which, in turn, programs Inrush according to Inrush=10A-Cload/C2. When the ramp voltage is within 1.2V of the regulated internal supply voltage, the controller will force the GATE terminal to a nominal 10V, the PWRGD pin will change to an active state, the Circuit Breaker is enabled and the circuit will transition to a low power sleep mode. When the voltage on the SENSE pin rises to 100mV, indicating an over current condition, the circuit breaker will trip in less than 5s. This time may be extended by the addition of external components. At any time during the start up cycle or thereafter, crossing the UV and OV limits (including hysteresis) will cause an immediate reset of all internal circuitry. When the input supply voltage returns to a value within the programmed UV and OV limits a new start up sequence will be initiated.
Design Information
Setting Under Voltage and Over Voltage Shut Down The UV and OV pins are connected to comparators with nominal 1.21V thresholds and 100mV of hysteresis (1.21V 50mV). They are used to detect under voltage and over voltage conditions at the input to the circuit. Whenever the OV pin rises above its high threshold (1.26V) or the UV pin falls below its low threshold (1.16V) the GATE voltage is immediately pulled low, the PWRGD pin changes to its inactive state and the external capacitor connected to the RAMP pin is discharged. Calculations can be based on either the desired input voltage operating limits or the input voltage shutdown limits. In the following equations the shutdown limits are assumed. The under voltage and over voltage shut down thresholds can be programmed by means of the three resistor divider formed by R1, R2 and R3. Since the input currents on the UV and OV pins are negligible the resistor values may be calculated as follows: UVOFF = VUVL = 1.16 = VEEUV (off ) x R2 + R3 R1 + R2 + R3 R3 R1 + R2 + R3 From the second equation for an OV shut down threshold of 65V the value of R3 may be calculated.
OVOFF = 1.26 = R3 =
65 x R3 500k
1.26 x 500k = 9.69k 65
The closest 1% value is 9.76k. From the first equation for a UV shut down threshold of 35V the value of R2 can be calculated.
UVOFF = 1.16 =
35 x ( R2 + R3) 500k
R2 = 1.16 x 500k - 9.76k = 6.81k 35
The closest 1% value is 6.81k. Then
R1 = 500k - R2 - R3 = 483k
OVOFF = VOVH = 1.26 = VEEOV (off ) x
Where |VEEUV(off)| and |VEEOV(off)| relative to VEE are Under & Over Voltage Shut Down Threshold points. If we select a divider current of 100A at a nominal operating input voltage of 50 Volts then
The closest 1% value is 487k.
R1 + R2 + R3 =
50V = 500k 100A
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HV301/HV311
Design Information, cont'd.
Undervoltage/Overvoltage Operation
GND
UVOFF UVON
VSENSE
10V C2 0.75nF 48V
10A
Cload
1:2
10A Isink RAMP terminal 10n=Cramp
mirror
GATE Termial Vsense Rsense
VIN
OVON OVOFF
5k Internal Circuitry
Pass Transistor
ON OFF
1.
Choose circuit breaker trip point eg. 8A as follows Rsense = 100 mV 100 mV = = 12.5m ICB 8
From the calculated resistor values the OV and UV start up threshold voltages can be calculated as follows:
2.
UVON = VUVH = 1.26 = VEEUV (on) x R2 + R3 R1 + R2 + R3 R3 R1 + R2 + R3
Choose inrush level, for example Inrush = 1A Inrush*Rsense 1A x 12.5m = = 2.5A 5k 5k
3. Calculate Isink =
OVON = VOVL = 1.16 = VEEOV (on) x
4. Calculate C2 discharge limit = 10A -Isink = 7.5A (typical) = iC 2 4a. Adjust for Auto -retry disable, if used Vt max 4V = 1.6A e.g. R disable 2.5M
Where |VEEUV(on)| and |VEEOV(on)| are Under & Over Voltage Start Up Threshold points relative to VEE. Then
VEEUV (on) = 1.26 x R1 + R2 + R3 R2 + R3 VEEUV (on) = 1.26 x 487k + 6.81k + 9.76k = 38.29V 6.81k + 9.76k And VEEOV (on) = 1.16 x R1 + R2 + R3 R3 VEEOV (on) = 1.16 x 487k + 6.81k + 9.76k = 59.85V 9.76k
e.g. iC 2 = 10A -Isink -1.6A In this example we assume Auto-retry is enabled so Auto ignore 1.6A, iC 2 = 10A -Isink = 7.5A 5. Note: i = C dv dt iC 2 = C 2 x dv dt Inrush = Cload x dv dt
Note VIN is fixed and VRAMP is constant during limiting dv dv across Cload = across C 2 (as they share a dt dt common node and their other terminals are fixed during inrush) iC x Cload iC2 Inrush = Inrush = 2 C2 Cload C2 by conservation of charge on RAMP Node iC2 = 7.5A
Therefore, the circuit will start when the input supply voltage is in the range of 38.29V to 59.85V.
Programming Inrush and ICB
Method 1: Inrush independent of ICB
10V C2 10A 7.5A 7.5A - + inrush
- +
Inrush =
7.5A x Cload 7.5A x Cload C2 = C2 Inrush
Vin
=
Cload=100F
7.5A x 100 nF = 750pF = 0.75nF 1A
0A
+K-
GATE RAMP
Cgd (DRAIN) Cdb
VSENSE
2.5A
0A 10n Vgs
+ -
Note that RAMP is protected by AC divider and Gate is clamped internally.
Cgs
gm(Vgs-Vt) VSENSE
5k dv on Cramp constant df during limiting so no current flowing into cap
Rsense=12.5mW
A092605
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HV301/HV311
Design Information, cont'd.
Programming Inrush and ICB, continued:
Method 2: Inrush = 1/2 ICB
Timing
contact bounce
GND
100mV 1. Choose ICB = , e.g. 2A RSENSE = 50m RSENSE 2. Inrush = 50mv 50mV , e.g. =1A RSENSE 50m
VIN VOUT
-48V
VOUT
VUVL
VIN
VGATE
3. Add compensation components from gate to drain if necessary to reduce peaking.
tSTART
VRAMP VGATE
VEE tTH
VRAMP
VGS(th)
VGATE
VGS(lim)
IIN
tPOR
90%
ILIM
tRISE tLIM
active
tPWRGD
PWRGD
inactive
i) start with 2nF from gate to source ii) increase to 10nF if needed iii) add 1k Series resistor from gate to capacitor if needed
Initialization
Limiting
Full On
The timing functions are defined by the following equations:
t START = 2.4
CRAMP I RAMP CRAMP I RAMP
tTH = VGS ( th )
t POR = t START + tTH t RISE CRAMP I RAMP R g fs - SENSE RFB 0.9 I LIMIT CLOAD I LIMIT
t LIMIT VIN
t PWRGD = VINT - VGS (LIMIT ) - 1.2
(
)C I
RAMP
RAMP
A092605
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HV301/HV311
Design Information, cont'd.
These equations assume that the load is purely capacitive and the following definitions apply. Start up Overload Protection Start up must be achieved within a nominal 100ms as indicated by the PWRGD pin transition to the active state or the circuit will reset and an automatic restart will initiate after 12s delay. If there is an output overload or short circuit during start up, the circuit will be in a current mode for the 100ms time limit. Circuit Breaker The circuit breaker will trip in less than 5s when the voltage on the SENSE pin reaches a nominal 100mV (2.0 x ILIMIT). A resistor in series with the SENSE pin and a capacitor connected between the SENSE and VEE pins may be added to delay the rate of voltage rise on the SENSE pin, thus permitting a current overshoot and delaying Circuit Breaker activation. Automatic Restart The Automatic Restart delay time is directly proportional to the capacitance at the RAMP pin. Automatic Restart sequence is activated whenever the 100ms timeout is reached during start up or the Circuit Breaker is tripped in low power sleep operating mode. Auto-retry can be approximated as an SSS-timer with 2.5A charge up and charge down currents through 28V, to a count of 256. Therefore, Cramp TAUTORETRY = 2 x 8 x 256 x Cramp 2.5 A
CRAMP is the external capacitor connected to the RAMP pin. IRAMP is the output current from the RAMP pin, nominally 10A, when the voltage drop on RSENSE resistor is zero. VINT is the internally regulated supply voltage and can range from 8.5V to 12V. VGS(th) is the gate threshold voltage of the external pass transistor and may be obtained from its datasheet. VGS(limit) is the external pass transistor gate-source voltage required to obtain the limit current. It is dependent on the pass transistor's characteristics and may be obtained from the transfer characteristics on the transistor datasheet. gfs is the transconductance of the external pass transistor and may be obtained from its datasheet. RFB is the internal feedback resistor and is nominally 5k. ILIMIT is the load current when the voltage drop on the RSENSE resistor is 50mV.
These equations may be used to calculate the minimum value of CRAMP for the most critical system performance characteristics. For maximum contact bounce duration protection choose a value for tPOR and use the following equation:
2.5A
2.5A
CRAMP
t xI = POR RAMP 2.4 + VGS ( th )
If control of PWRGD active delay is the critical system parameter, then choose a value for tPWRGD and use the following equation:
C RAMP = t PWRGD x I RAMP VINT - VGS(limit) - 1.2
Due to the 2.5A max charge current a resistor which draws more than 2.5A below 8V will disable the autoretry. Try to keep this resistor as big as possible, e.g. 2.5my, for most MOSFETs with max Vt of 4V this will vary the 10A current source by only 4/2.5my=1.6A.
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HV301/HV311
Application Information
Supported External Pass Devices The HV301 and HV311 are designed to support N-Channel MOSFETs and IGBTs. Selection of External Pass Devices Since the current limit is likely to be set just slightly higher than maximum continuous load current in a typical system, the continuous current rating of the device will have to be at least equal to the current limit value. The RDS(ON) of the device is likely to be selected based on allowable voltage drop after the hot swap action has been completed. Thus the continuous power dissipation rating of the device can be determined from the following equation:
2 PCONT = RDS (ON ) x I LIMIT
Paralleling External Pass Transistors Due to variations in threshold voltages and gain characteristics between samples of transistors reliable 50% current sharing is not achievable. Some measure of paralleling may be accomplished by adding resistors in series with the source of each device; however, it will cause increased voltage drop and power dissipation.
Paralleling of external Pass devices is not recommended!
If a sufficiently high current rated external pass transistor cannot be found then increased current capability may be achieved by connecting independent hot swap circuits in parallel, since they act as current sources during the load capacitor charging time when the circuits are in current limit. For this application the HV301 with active high PWRGD is recommended where the PWRGD pins of multiple hot swap circuits can be connected in a wired OR configuration.
The peak power rating may be calculated from the following equation:
PPEAK = VIN x I LIMIT
Given these values an external pass transistor may be selected from the manufacturers data sheet. Selection of Current Sense Resistor The power rating of the sense resistor must be greater than 2 Iload x R , where Iload is the normal maximum operating load. Kelvin Connection to Sense Resistor Physical layout of the printed circuit board is critical for correct current sensing. Ideally trace routing between the current sense resistor and the VEE and SENSE pins should be direct and as short as possible with zero current in the sense traces. The use of Kelvin connection from SENSE pin and VEE pin to the respective ends of the current sense resistor is recommended.
To To VEE SENSE Pin Pin
To Negative Terminal of Power Source
Sense Resistor
To Source of MOSFET
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HV301/HV311
PWRGD Output It is critical to have a detailed understanding of the ENABLE input circuitry of the load (DC/DC PWM Converter) in order to make the correct choice between the HV301 and HV311. Many DC/DC PWM Converters reference their ENABLE inputs to the negative input terminal. If the ENABLE input is active LOW then the HV311 can be directly connected as shown below (Application Circuit 1) since the open drain PWRGD output is in a High-Z state until the external MOSFET is fully turned on and the potential on the negative input of the converter is essentially the same as the VEE pin of the HV311.
GND
8 VDD PWRGD 1 3 UV + Cload ENABLE +5V
R1 487kW R2 6.81kW 2 R3 9.76kW
RAMP VEE SENSE GATE
HV311
OV
-
DC/DC PWM CONVERTER
COM
7 C1 10nF -48V
4
5
6
R4 12.5mW
Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 1
In some applications the PWRGD signal is used to activate load circuitry on the isolated output side of the DC/DC PWM Converter. In this situation an optocoupler is needed to provide the required isolation as shown below in Application Circuit 3.
However, if the DC/DC PWM Converter with the ENABLE input circuit configuration was active HIGH, then the apparent choice of the HV301 would result in the creation of a current path through the protective diode clamp of the ENABLE input and the PWRGD output MOSFET of the HV301. For this situation the HV311 should be used as shown below in Application Circuit 2.
GND
8 VDD PWRGD 1 + 3 UV
R1 487kW R2 6.81kW R3 9.76kW
ENABLE
+5V
2
HV311
OV
Cload DC/DC PWM CONVERTER COM
RAMP VEE SENSE GATE
7 C1 10nF -48V
4
5
6
R4 12.5mW
Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO. 10
Application Circuit 2
A092605
HV301/HV311
Optocoupler GND 8 VDD R1 487kW 3 R2 6.81kW 2 R3 9.76kW RAMP 7 C1 10nF -48V R4 12.5mW Q1 IRF530 VEE 4 SENSE GATE 5 6 OV UV PWRGD 1 Rload
ENABLE
+5V
HV311
Cload DC/DC PWM CONVERTER COM
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 3
When the details of the load ENABLE circuitry is not known, using an optocoupler always provides a safe solution (Application Circuit 4).
Filtering Voltage Spikes on Input Supply In some systems over voltage spikes of very short duration may exist. For these systems a small capacitor may be added from the OV pin to the VEE pin to filter the voltage spikes (Application Circuit 5).
Optocoupler
GND
8 VDD PWRGD / PWRGD 1
R1 487kW 3 R2 6.81kW 2 R3 9.76kW RAMP 7 C1 10nF -48V R4 60mW Q1 IRF530 VEE 4 SENSE GATE 5 6 OV UV
ENABLE / ENABLE
+5V
HV311
Cload DC/DC PWM CONVERTER COM
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO. 11
Application Circuit 4
A092605
HV301/HV311
GND 8 VDD R1 487kW R2 6.81kW R3 9.76kW RAMP 7 C2 -48V
C1 10nF
PWRGD / PWRGD
1 ENABLE / ENABLE +5V
3
UV
2
OV
HV301/ HV311
VEE 4 SENSE GATE 5 6
Cload DC/DC PWM CONVERTER COM
R4 12.5mW
Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 5
Unfortunately this will also cause some delay in responding to UV conditions. If this UV delay is not acceptable, then separate resistor dividers can be provided for OV and UV with a capacitor connected from OV pin to the VEE pin (Application Circuit 6).
Using Short Connector Pin In some systems short connector pins are used to guarantee that the power pins are fully mated before the hot swap control circuit is enabled. For these systems the positive (VDD) end of the R1, R2, and R3 resistor divider should be connected to the short pin (Application Circuit 7).
GND
8 VDD PWRGD / PWRGD
1 ENABLE / ENABLE +5V
R1 475k R2 16.2k R3 511k
3
UV
HV311
2 OV
Cload DC/DC PWM CONVERTER COM
R4 10k RAMP 7 C2 -48V C1 10nF R5 12.5m Q1 IRF530 VEE 4 SENSE GATE 5 6
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 5
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Long Pin GND Short Pin GND R1 487k 8 VDD PWRGD / PWRGD
HV301/HV311
1 ENABLE / ENABLE +5V
3
UV
R2 6.81k R3 9.76k
2
OV
HV301/ HV311
VEE 4 SENSE GATE 5 6
Cload DC/DC PWM CONVERTER COM
RAMP 7 C1 10nF -48V Long Pin
R4 12.5m
Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 6
If separate resistor dividers are used for OV and UV, then only the positive (VDD) end of the UV resistor divider should be connected to the short pin (Application Circuit 8). If a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully
mated before the hot swap control circuit is enabled and a single resistor divider string (R1, R2 and R3) is used, then a 6.2V to 10V zener diode must be connected from the UV pin to the VEE pin, as seen below in Application Circuit 9.
Long Pin GND Short Pin GND R1 475K 8 VDD PWRGD / PWRGD 1 3 R3 511K 2 R4 10K RAMP 7 VEE SENSE 5 GATE 6 OV ENABLE / ENABLE UV +5V
R2 16.2K
HV311
Cload DC/DC PWM CONVERTER COM
4
-48V Long Pin
C1 10nF R5 12.5m Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO. 13
Application Circuit 8
A092605
HV301/HV311
Long Pin GND 8 VDD R1 487k 3 R2 6.81k R3 9.76k RAMP 7 Short -48V Pin Long Pin R4 12.5m Q1 IRF530 6.2V C1 10nF -48V VEE 4 SENSE GATE 5 6 UV PWRGD / PWRGD
1 ENABLE / ENABLE +5V
2
HV311
OV
Cload DC/DC PWM CONVERTER COM
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 9
If a system requires the use of a short connector pin on the negative supply lead to guarantee that the power pins are fully mated before the hot swap control circuit is enabled and uses separate resistor dividers for UV and OV, then a 6.2V to 10V zener diode must be connected from the OV pin to the VEE pin and only the OV divider should be connected to the short pin (Application Circuit 10).
Long Pin GND 8 VDD R1 475k 3 UV R2 16.2k R3 511k 2 OV R4 10k RAMP 7 Short -48V Pin Long Pin 6.2V C1 10nF R5 12.5m VEE 4
Increasing Under Voltage Hysteresis If the internally fixed under voltage hysteresis is insufficient for a particular system application, then it may be increased by using separate resistor dividers for OV and UV and providing a resistor feedback path from the GATE pin to the UV pin (Application Circuit 11).
PWRGD / PWRGD
1 ENABLE / ENABLE +5V
HV301/ HV311
Cload DC/DC PWM CONVERTER COM
SENSE GATE 5 6
-48V
Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 10
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14
HV301/HV311
GND 8 VDD R1 475k 3 R2 16.2k R3 511k 2 R4 10k RAMP 7 R6 C1 10nF R5 12.5m Q1 IRF530 VEE 4 SENSE GATE 5 6 OV UV PWRGD / PWRGD 1 ENABLE / ENABLE +5V
HV301/ HV311
Cload DC/DC PWM CONVERTER COM
-48V
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 11
Reverse Polarity Protection The UV and OV pins are protected against reverse polarity input supplies by internal clamping diodes and the fault currents are sufficiently limited by the impedance of the external resistor divider, however, a low current diode with a 100V breakdown rating must be inserted in series with the VDD pin. This method (shown in Application Circuit 12) will protect the hot swap control circuit however, due to the intrinsic diode in the external MOSFET, the load will not be protected from reverse polarity voltages.
GND 8
D1
VDD R1 487k 3 R2 6.81k 2 OV R3 9.76k RAMP 7 C1 10nF -48V VEE 4 UV
PWRGD / PWRGD
1 ENABLE / ENABLE +5V
HV311
Cload DC/DC PWM CONVERTER COM
SENSE GATE 5 6
R4 12.5m
Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 12
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15
HV301/HV311
Redundant Supplies Many systems use redundant primary power supplies or battery backup. When redundant AC powered sources are used they are generally diode OR'ed to the load on the hot terminal. For these systems, the use of independent hot swap controllers is recommended with the diode OR'ing provided after the hot swap controllers. The HV311 is ideally suited for such applications since two or more active low PWRGD signals can be connected to a single active low ENABLE pin, thus enabling the load as long as at least one primary power source is available. By adding low current 100V diodes in series with the VDD pins, full reverse polarity protection on either power source is also provided (Application Circuit 13).
GND 8
D2
VDD R1 487k 3 PS1 R2 6.81k 2 OV R3 9.76k RAMP 7 VEE 4 UV
PWRGD 1
HV301/ HV311
SENSE GATE 5 6
C1 10nF -48V R4 60m D2 8 VDD R1 487k 3 PS2 R2 6.81k 2 R3 9.76k RAMP 7 VEE 4 SENSE GATE 5 6 OV UV PWRGD 1 ENABLE / ENABLE +5V Q1 IRF530 D1
GND
HV301/ HV311
Cload DC/DC PWM CONVERTER COM
C1 10nF -48V R4 60m Q1 IRF530 D1
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 13
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HV301/HV311
Use with Negative Ground The HV301 and HV311 may be used with many positive ground systems where DC/DC PWM Converters have isolated outputs and their inputs need not be ground referenced (Application Circuit 14). Current Limit Stability (Method 2 (Servo) Only) The closed loop current mode control system used in the HV301/ HV311 is very stable, especially when driving MOSFETs with high gate capacitances (CISS). However, a peaking in ILIMIT near the end of the current limit may be noted with some MOSFETs. The current control loop can be frequency compensated to eliminate this peaking by adding a series connected capacitor and resistor between the gate and source of the external MOSFET. The recommended starting values for C and R are 10nF and 1K. These compensation values should be verified by board level testing, which may yield satisfactory results with reduced component values.
+48V
8 VDD PWRGD / PWRGD 1
R1 487k R2 6.81k R3 9.76k
3
ENABLE/ ENABLE UV
+5V
2
OV
HV301/ HV311
Cload COM DC/DC PWM CONVERTER
RAMP 7
VEE 4
SENSE GATE 5 6
C1 10nF GND R4 12.5m Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO.
Application Circuit 14
A092605
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HV301/HV311
Extending Circuit Breaker Delay Connecting a resistor in series with the SENSE pin and a capacitor between the SENSE and VEE pins as shown in the following diagram may be used to extend the Circuit Breaker delay time beyond the 5s internally set delay time (Application Circuit 15). The time delay achievable by this method is limited since this delay circuit will also effect the current control feedback loop and will result in a current overshoot during the external pass device turn on transition to current limit. If the time delay required for the Circuit Breaker causes excessive current overshoot during the turn on transition then the following circuit may be used, where the RC filter is switched on after the completion of the current limit control function of the hot swap controller.
GND
8 VDD R1 487k PWRGD / PWRGD 1
3
ENABLE/ ENABLE UV
+5V
R2 6.81k R3 9.76k
2
OV
HV301/ HV311
Cload DC/DC PWM CONVERTER COM
RAMP 7
VEE 4
SENSE GATE 5 6
-48V
C2 R4 12.5m
R5
Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO. Latched Operation For those applications that need to disable the automatic retry capability, the following circuit disables the auto retry feature.
Application Circuit 15
GND
8 VDD R1 487k R2 6.81k R3 9.76k VEE 4 SENSE GATE 5 6 RAMP 7 PWRGD / PWRGD 1 ENABLE / ENABLE +5V
3
UV
HV301 / HV311
2 OV
Cload DC/DC PWM CONVERTER COM
2.5MW
-48V R4 12.5m Q1 IRF530
Note: capacitor may be needed to slow PWRGD dv/dt if gate oscillations around are observed when VIN is close to OVLO. 18
Application Circuit 17
A092605
HV301/HV311
Package Dimensions
0.192 0.005 (4.89 0.11)
D
Inches (Millimeters)
H
0.236 0.008 (5.99 0.20)
E
H1
0.154 0.004 (3.91 0.10)
0.193 0.012 (4.90 0.30)
7 (4 PLCS) 0.010 0.002 C (0.254 0.051)
A
h
0.020 0.009 (0.508 0.229)
45
L1
0.061 0.008 (1.55 0.20)
0 - 8
e A1 B
0.007 0.003 (0.178 0.076)
0.050 TYP. (1.20)
0.016 0.002 (0.406 0.05)
L
0.035 0.015 (0.889 0.381)
0.0275 0.0025 (0.698 0.064)
Circled letters (e.g. B denote JEDEC reference dimensons.
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Technical Update / Alert
This alert applies to the HV301, HV302, HV311, and HV312 Hotswap Controllers
The internal circuit breaker may trip unintentionally in situations when the voltage at the VDD pin rises slowly as power is applied. This unintended tripping of the circuit breaker causes the power-on sequence to be delayed by an additional Automatic Restart Delay. The extra delay can be observed by viewing the voltage waveform at the RAMP pin. Subsequent to this delay, this device will perform a regular start-up, thereby providing power to the load.
HV301/HV311
The inadvertant tripping of the circuit breaker does not occur when the input voltage slew rate is greater than 400V per ms. In a typical hotswap application, the rise of the input voltage occurs in a couple of microseconds, and the slew rate is well in excess of of the value necessary to cause tripping of the circuit breaker.
If technical assistance is required, please contact our applications department by e-mail at apps@supertex.com, or by telephone at 408-222-4895.
Doc.# DSFP - HV301/HV311 A092605
A092605
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